1. Field of the Invention
The present invention relates to a flat panel display technology, and in particular to thin film transistor (TFT) devices in driving circuit and pixel regions, and a method for fabricating a system for displaying images having the TFT devices.
2. Description of the Related Art
The demand for active-matrix flat panel displays, such as active matrix liquid crystal displays (LCDs), has increased rapidly in recent years. LCDs typically employ thin film transistors (TFTs) as pixel and driving circuit switching elements which are classified as amorphous silicon (a-Si) TFTs and polysilicon TFTs according to the materials used as an active layer. Compared with a-Si TFTs, polysilicon TFTs have the advantages of high carrier mobility, high driving-circuit integration, and are often applied to high-speed operation applications. One of the major drawbacks of polysilicon TFTs is OFF-state leakage current, causing charge loss in LCDs. Seeking to address this problem, conventional lightly doped drain (LDD) structures have been used to reduce the drain junction field, thereby reducing leakage current.
FIGS. 1A to 1D illustrate a conventional method for fabricating an n-type thin film transistor device for a flat panel display (FPD). In FIG. 1A, a substrate 100 is provided. The substrate 100 comprises a driving circuit region I and a pixel region II. A buffer layer 102 is deposited on the substrate 100, which may serve as an adhesion layer or a contamination barrier layer between the substrate 100 and a subsequent active layer. First and second active layers 103 and 104 are formed on the buffer layer in the driving circuit region I and the pixel region II, respectively. The first and second active layers 103 and 104 may comprise polysilicon and may be formed by conventional low temperature polysilicon (LTPS) technology. Boron ion implantation 10 is performed on the first and second active layers 103 and 104 for channel doping.
In FIG. 1B, a masking pattern layer 106 is formed on the substrate shown in FIG. 1A, to cover portions of the first and second active layers 103 and 104, respectively, for definition of a source/drain region. Heavy-ion implantation 12 for n-type doping is performed to form source/drain regions 103a and 104a in the first and second active layers 103 and 104, respectively.
After removal of the unnecessary masking pattern layer 106, a gate dielectric layer 108 and a metal layer 110 are successively formed on the substrate shown in FIG. 1B, as shown in FIG. 1C. Next, a masking pattern layer 112 is formed on the metal layer 110 above the first and second active layers 103 and 104 for gate definition.
The metal layer 110 uncovered by the masking pattern layer 112 is etched to form gate layers 113 and 114 overlying the first and second active layers 103 and 104, as shown in FIG. 1D. Typically, the gate layers 113 and 114 do not overlap the underlying source/drain regions 103a and 104a in order to define lightly doped drain (LDD) regions in subsequent step. Thereafter, light-ion implantation 14 for n-type LDD doping is performed using the gate layers 113 and 114 as implanting masks, to form channel regions 103c and 104c (i.e. undoped regions under the gate layers 113 and 114) and lightly doped regions 103b and 104b serving as LDDs in the first and second active layers 103 and 104, completing the fabrication of the TFTs in the driving circuit region I and the pixel region II.
In the conventional thin film transistor device, the TFTs in the driving circuit region I and the pixel region II are fabricated at the same time and by the same process. Therefore, the length d1 of the lightly doped region 103b is substantially equal to the length d2 of the lightly doped region 104b. Typically, it is desirable to design pixel TFTs with low leakage current and driving TFTs with high electron mobility (fast response). However, it is difficult to fabricate TFTs with low leakage for a pixel region and high electron mobility for a driving circuit region because both leakage and electron mobility are inversely relative to the length of LDD. That is, the conventional thin film transistor devices cannot have TFTs with low leakage for a pixel region and high electron mobility for a driving circuit region due to LDD in both the pixel and driving circuit regions being the same length. Moreover, in a conventional thin film transistor device, lithography is employed to define the location and size of the LDD region. Thus, it is difficult to further reduce the length of the LDD to improve electron mobility due to the limitations of lithography.
Thus, there exists a need in the art for development of an improved thin film transistor device which has different TFT electrical characteristics in the driving circuit and pixel regions, thereby providing driving TFTs with high electron mobility and pixel TFTs with low leakage.